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DDR_interface
- 高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 -High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS
RS232_Controller
- This project is a RS232 Controller used to communicate two devices.
cfft_latest.tar
- VHDL 1024 FFT PROJECT
CPU
- 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended
20081209_Test_maus
- Its project to move your mouse cursor on a vga monitor. it is very funny -)-Its project to move your mouse cursor on a vga monitor. it is very funny -)
noise_gate
- unfinished vhdl project
EP1C3_12_7_SPCTR
- 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
EP1C3_12_1_2_MOTO
- 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写，压缩包里是Quartus下的工程。-FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
music
- 用CPLD做音乐发生器，实现2首歌播放控制，用ise编译过的工程-CPLD to do with music generator, two songs to play to achieve control, compiled with the project ise
Eat_beans_on_the_8086_games
- 本项目在FPGA上生成8086指令兼容的软核以及外设，并在此基础上跑通pc机上古老但是仍然有趣的吃豆子PACMAN游戏， 作为本科微机原理课程的实验。 通过本项目，学生可以学习到8086的基本结构， 在TurboC下如何进行嵌入式C语言编程，汇编语言， 计算机组成等基本原理， 有独立设计基于8086的SOC软硬件的能力。-The project generated in the FPGA on the 8086 Directive, as well as soft-core-compatible
4_Bit_Alu_vhdl
- Complete VHDL Code for a 4 BIT ALU PROJECT
ref3
- nexys 2 vhdl reference project for uart
EP1C3_81_SCHK
- 序列检测器设计 这里面是一个完整的工程可以直接适用-Sequence detector design there is a complete project can be applied directly
Freq_4
- 伺服电机编码器四倍频源程序，已经在工程中应用。非常有用。-it is important,it has been use in my project.i hope it is useful to everyone
sim_usb_full_interface_tb
- FTDI245B usb project
TrafficLight
- 用vhdl写的交通灯程序，压缩包内有整个工程文件-With the traffic lights to write vhdl procedure, compressed package files have the whole project
ethernet
- ：提出了一种基于FPGA 实现嵌入式三态(10MB/100MB/1 000MB)以太网的设计方案，分别从硬件和软件方面介绍了使用FPGA 进 行嵌入式系统设计的方法，编写了一个控制系统进行10MB/100MB/1000MB 自切换程序，并在工程中得以实现。-: This paper presents a FPGA-based Embedded Tri-State (10MB/100MB/1 000MB) Ethernet design, from hardware and software,
pinlvji
- 等精度频率计设计，很好的源代码，附上工程文件，在quartus5.0以上版本即可运行。-Design accuracy, such as frequency meter, a good source code, attached to the project document, in the above quartus5.0 to run.
rls
- 是二阶RLS自适应均衡的实现，采用V—LOG编写而成，是从工程中截取的 可以直接应用-Second-order RLS adaptive equalizer is the realization of the use of V-LOG prepared is intercepted from the project can be applied directly
spi
- 此程序是一个完整的项目工程，包括c-c++程序和VHDL程序 -This procedure is a complete project, including the c-c++ program and VHDL procedures